1. Field of the Invention
The present invention relates to a semiconductor device, and particularly to a structure for connecting semiconductor elements of a semiconductor integrated circuit and wiring layers.
2. Description of the related Art
A semiconductor integrated circuit has recently been moved toward increasingly greater densities, and the tendency has been toward further narrowing of the width of each wiring and the interval between the wirings. The development thereof has been put forward with the aim of obtaining an integrated circuit device whose design rule is of a 0.15 xcexcm-class.
FIG. 30 is a partly see-through plan view of a conventional integrated circuit device. FIG. 31 is a cross-sectional view of the conventional integrated circuit device as viewed in the form of a section taken along line XXXIxe2x80x94XXXI of FIG. 30.
In FIGS. 30 and 31, reference numeral 200 indicates a semiconductor integrated circuit, e.g., an SRAM, i.e., a partial CMOS thereof herein. Reference numeral 202 indicates a silicon substrate, reference numeral 204 indicates an NMOS constituting the semiconductor integrated circuit 200, reference numerals 204a and 204b indicate source/drain regions of the NMOS 204, and reference numeral 204c indicates a gate electrode of the NMOS 204. In FIG. 31, reference numeral 204d indicates a gate insulating film of the NMOS 204, and reference numeral 204e indicates an active region lying between the source/drain regions 204a and 204b. 
Reference numeral 206 indicates a PMOS constituting the semiconductor integrated circuit 200, reference numerals 206a and 206b indicate source/drain regions of the PMOS 206, and reference numeral 206c indicates a gate electrode of the PMOS 206. In FIG. 31, reference numeral 206d indicates a gate insulating film of the PMOS 206, and reference numeral 206e indicates an active region lying between the source/drain regions 206a and 206b. 
In FIG. 31, reference numerals 208 indicate isolating oxide films, reference numeral 210 indicates an etching stopper layer, and reference numeral 212 indicates an interlayer insulating film. In FIGS. 30 and 31, reference numerals 214 indicate contact holes, reference numerals 214a, 214b, 214c, 214d and 214e indicate connecting conductors for the contact holes, and reference numerals 216 (216a, 216b and 216c) indicate wiring layers.
Incidentally, FIG. 30 is illustrated with the etching stopper layer 210 and the interlayer insulating film 212 being omitted therefrom.
FIG. 32 is a partly see-through plan view of another conventional integrated circuit device. FIG. 33 is a cross-sectional view of the conventional integrated circuit device as viewed in the form of a section taken along XXXIIIxe2x80x94XXXIII of FIG. 32.
In FIGS. 32 and 33, reference numeral 220 indicates a semiconductor integrated circuit, e.g., Flash (non-volatile memory) comprised of an NMOS, i.e., a part thereof herein.
In FIGS. 32 and 33, the same reference numerals as those shown in FIGS. 30 and 31 respectively indicate the same or equivalent ones. They are similar even in the case of the following individual drawings.
Reference numerals 222 indicate connecting diffusion regions, which are used to connect source regions of individual NMOSs to one another for the purpose of holding ones of the source/drain regions of NMOSs 204, e.g., the source regions at equal potentials. In FIG. 32, the connecting diffusion regions 222 are diagonally shaded to clearly define the differences between the same regions and other portions without being intended for the representation of the section. Reference numerals 224 (224a, 224b and 224c) indicate wiring layers.
FIG. 32 is illustrated with an etching stopper layer 210 and an interlayer insulating film 212 being omitted therefrom.
In each of the semiconductor integrated circuit 200 and the semiconductor integrated circuit 220 respectively having such structures, the connecting conductors 214a, 214b, 214c, 214d and 214e of the contact holes 214, which are respectively connected to the source/drain regions 204a, 204b, 206a and 206b and the gate electrodes 204c provided on the silicon substrate 202, and the wiring layers 216 are formed of a complex film of a high melting-point metal comprising a titanium film, a titanium nitride film and a tungsten film in the same process.
However, the metal wirings for forming the connecting conductors 214a, 214b, 214c, 214d and 214e and the wiring layers 216 in the same process by using the complex film formed of such a high melting-point metal have a problem that a phenomenon occurs wherein when a design rule reaches 0.15 xcexcm or less, an etching gas for dry etching is hard to reach a narrow etching region between the wirings with a decrease in etching width between the wirings, thus causing the inconvenience that each etching residual of the high melting-point metal takes place.
Further, the semiconductor integrated circuit 220 needs to connect the sources of the respective NMOSs for the purpose of holding ones of the source/drain regions of the respective arranged NMOSs 204, e.g., the sources at equal potentials. However, they are connected to one another by the connecting diffusion regions 222 because it is hard to provide the wiring layers in parallel with the gate electrodes 204c. However, there is a possibility that the connections thereof by the connecting diffusion regions 222 will cause inconvenience that a resistance value suddenly increases when the width of each connecting diffusion region 222 becomes narrow, and when a source resistance increases, device characteristics such as a reduction in the speed due to an increase in time constant, a reduction in the drive current of each transistor, etc. will be degraded. For instance, a method of implanting an impurity to each source region in high concentrations is also considered. However, the present method is accompanied by a problem that a leak characteristic of a pn junction is degraded.
Incidentally, Japanese Patent Laid-Open No. Hei 6(1994)-112408, Japanese Patent Laid-Open No. 2000-22080 and Japanese Patent Laid-Open No. Hei 8(1996)-316320 respectively have described an example of a MISFET having an interlayer insulating film provided as one layer and having a structure wherein a gate electrode and a source region are electrically connected to each other.
The present invention has been made to solve the foregoing problems. It is an object of the present invention to provide a semiconductor device equipped with a plurality of MOS type elements, which has such a configuration that even if a design rule is rendered small, the interval between wiring layers on an interlayer insulating film can be widened.
According to one aspect of the invention, there is provided a semiconductor device comprising: a semiconductor substrate having one main surface; a first semiconductor element having source and drain regions provided on the main surface of the semiconductor substrate, and a gate electrode provided on an active region lying between the source and drain regions with an insulating film interposed therebetween; a second semiconductor element provided with each of isolation regions being interposed between the first semiconductor element and the second semiconductor element, having source and drain regions provided on the main surface of the semiconductor substrate, and a gate electrode provided on an active region lying between the source and drain regions with an insulating film interposed therebetween; a first insulating film which is provided on the semiconductor substrate with the first and second semiconductor elements interposed therebetween and has a through hole extending via the source region or drain region of the first semiconductor element and the source region or drain region of the second semiconductor element; a first wiring layer which is buried in the through hole of the first insulating film and connects the source region or drain region of the first semiconductor element and the source region or drain region of the second semiconductor element; and a second insulating film which covers the first wiring layer and is provided on the first insulating film, and which has a surface on which second wiring layers are provided.
Accordingly, present invention enables to prevent a yield reduction due to the failure of the formation of each second wiring layer, since the first wiring layer connecting the source region or drain region of the first semiconductor element and the source region or drain region of the second semiconductor element is covered with the second insulating film the wiring-to-wiring pitch between the second wiring layers can be rendered wide. In its turn, an inexpensive and high-reliable semiconductor device can be constructed.
Other objects and advantages of the invention will become apparent from the detailed description given hereinafter. It should be understood, however, that the detailed description and specific embodiments are given by way of illustration only since various changes and modifications within the scope of the invention will become apparent to those skilled in the art from this detailed description.